The present invention relates generally to the fabrication of integrated circuits and, in particular, to techniques for fabricating integrated circuits incorporating insulating layers such as gate oxides having different thicknesses.
Integrated circuits incorporating active elements such as metal-oxide-semiconductor (MOS) devices that are operated from multiple power supplies are being developed for various applications. Examples of such integrated circuits include dual gate CMOS circuits, peripheral circuits for non-volatile memory and circuits for driving liquid crystal flat panel displays, among others. Such circuits can include active elements that require a high supply voltage and other elements for which a low supply voltage is sufficient. In general, a high supply voltage may be required for high performance, high speed circuit elements, whereas a low supply voltage may be sufficient for low speed circuit elements on the same integrated circuit chip. For example, in some applications, a high supply voltage of 5 volts (V) can be used with a corresponding low supply voltage of 3.3 V.
Typically, MOS devices or other circuit elements that are to be operated from the high supply voltage are formed so that their gate oxide is relatively thick. Conversely, circuit elements that are to be operated from the low supply voltage are formed with a relatively thin gate oxide.
Although various techniques have been employed in the formation of the different oxide layers, a fabrication process which results in an integrated circuit having multiple gate oxides of different thicknesses as well as with improved electrical properties is desirable.